Evaluation Techniques for Mapping IPs on FPGAs
نویسندگان
چکیده
منابع مشابه
Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping
In this paper, we present new Boolean matching methods for lookup table (LUT)-based programmable logic blocks (PLBs) and their applications to PLB architecture evaluations and field programmable gate array (FPGA) technology mapping. Our Boolean matching methods, which are based on functional decomposition operations, can characterize functions for complex PLBs consisting of multiple LUTs (possi...
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